diff options
| author | Sam Protsenko <[email protected]> | 2024-06-20 18:13:37 -0500 |
|---|---|---|
| committer | Herbert Xu <[email protected]> | 2024-06-28 11:35:48 +1000 |
| commit | e003d67067043488595f33f3a82230a4281686ca (patch) | |
| tree | d038234727fab103cfd2146e3df3c8ce10d0479c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 81da8056e92bd255178413d36382653ed5a1a230 (diff) | |
hwrng: exynos - Implement bus clock control
Some SoCs like Exynos850 might require the SSS bus clock (PCLK) to be
enabled in order to access TRNG registers. Add and handle the optional
PCLK clock accordingly to make it possible.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Anand Moon <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions