diff options
| author | Bard Liao <[email protected]> | 2024-04-11 17:03:47 -0500 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-04-14 16:54:32 +0900 |
| commit | dcc2cd8000d11a046680a7476b0d96b0b956454a (patch) | |
| tree | 81ea69b31300b067be0cb4f72b8e6bdded17ab8c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ca571e5a2e45b1a4113af2370fd1cf895f0b46d4 (diff) | |
ASoC: Intel: sof_rt5682: use RT5682S_PLL1 if needed
When 96KHz sample rate is used, and MCLK is 24.576MHz, we will need
pll_in = 24576000 and pll_out = 49152000 which is not supported by
RT5682S_PLL2. Use RT5682S_PLL1 in this case.
We don't test sample rate because RT5682S_PLL2 doesn't support 24.576MHz
input and in the MCLK = 24.576MHz, sample rate = 48KHz case, i.e.
pll_in == pll_out, PLL will not be used at all.
Reviewed-by: Ranjani Sridharan <[email protected]>
Signed-off-by: Bard Liao <[email protected]>
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions