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| author | Jerome Brunet <jbrunet@baylibre.com> | 2019-05-13 14:31:11 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2019-05-20 12:18:55 +0200 |
| commit | dc4e62d373f881cbf51513296a6db7806516a01a (patch) | |
| tree | 188605959275fc3943f12417ec03e53506d79c18 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8925dbd03bb29b1b0de30ac4e02c18faf8ddc9db (diff) | |
clk: meson: axg: spread spectrum is on mpll2
After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions