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| author | Miquel Raynal <[email protected]> | 2021-10-15 10:14:31 +0200 |
|---|---|---|
| committer | Lee Jones <[email protected]> | 2021-10-20 17:24:53 +0100 |
| commit | c4359f750a1e9e2665690171211645e7fe0095f8 (patch) | |
| tree | 056ebd0664f91914efb615ce63edf4473e8dbfd0 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 36e48f07ba2ba2aad98040df5e63a992a1eccba1 (diff) | |
mfd: ti_am335x_tscadc: Reword the comment explaining the dividers
The comment misses the main information which is that we assume that a
sample takes 15 ADC clock cycles to be generated. Let's take the
occasion to rework a little bit this comment.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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