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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2024-06-12 09:54:28 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-07-03 16:44:49 +0200 |
| commit | c171186c177970d3ec22dd814f2693f1f7fc1e7d (patch) | |
| tree | 242fc8438c003e9a5358c607ea963d538f97600e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 04f38d1a4db017f17e82442727b91ce03dd72759 (diff) | |
MIPS: csrc-r4k: Refine rating computation
Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level mips_hpt_frequency.
Cap rating of csrc-r4k into 299 to ensure it doesn't go into
"Desired" range, given all the drama we have with CP0 count
registers (SMP sync, behaviour on wait etc).
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions