diff options
| author | Imre Deak <[email protected]> | 2019-04-25 21:52:52 +0300 |
|---|---|---|
| committer | Imre Deak <[email protected]> | 2019-05-02 17:15:09 +0300 |
| commit | bd60a562906b2dfa6db4e9165c1498ea25db0587 (patch) | |
| tree | f179c259905bccc94b368ef3d82f11446be7e5ce /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 3904fb78a80da64d7fd1a4f270725a6d4272c86f (diff) | |
drm/i915/icl: Factor out combo PHY lane power setup helper
Factor out the combo PHY lane power configuration code to a separate
helper; it will be also needed by the next patch adding the same
configuration for DDI ports.
Add support for DDI ports and lane reversal as preparation for the next
patch.
The PWR_DOWN_LN_1 value is unspecified in the BSpec register description
so remove it.
v2:
- Fix up the wrong assumption that the encodings are the same for DDI
and DSI ports. (Jani)
v3:
- Use intel_ instead of icl_ prefix. (Jani)
- Add required headers to intel_combo_phy.h after the upstream header
refactoring.
Cc: Jani Nikula <[email protected]>
Cc: Madhav Chauhan <[email protected]>
Cc: Ville Syrjala <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> (v2)
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions