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| author | Jonathan Cameron <[email protected]> | 2022-05-08 18:55:49 +0100 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2022-06-14 11:53:12 +0100 |
| commit | b990cdfe7536a8da7e134d516350402981300016 (patch) | |
| tree | 867c7e56e7634662bb09401c22ffa064764f8e86 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | b1d3a806630dbbf3b4d75a2e850adccf4f4439e7 (diff) | |
iio: adc: ad7266: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to reflect that DMA safety 'may' require separate
cachelines.
Fixes: 54e018da3141 ("iio:ad7266: Mark transfer buffer as __be16")
Signed-off-by: Jonathan Cameron <[email protected]>
Acked-by: Nuno Sá <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions