diff options
author | Tony Lindgren <[email protected]> | 2021-02-05 15:45:31 +0200 |
---|---|---|
committer | Daniel Lezcano <[email protected]> | 2021-02-15 21:18:32 +0100 |
commit | b57b4b4d4ef9c2ecb169775815bebab0890cda50 (patch) | |
tree | c5bffc5a536ee5c05c824398e62c333430b5e0bd /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 73da3f0cca94555d08d62b60ec9b8b9582bc1313 (diff) |
thermal: ti-soc-thermal: Skip pointless register access for dra7
On dra7, there is no Start of Conversion (SOC) register bit and we have an
empty bgap_soc_mask in the configuration for the thermal driver. Let's not
do pointless reads and writes with the empty mask.
There's also no point waiting for End of Conversion bit (EOCZ) to go high
on dra7. We only care about it going down, and are now mostly timing out
waiting for EOCZ high while it has already gone down.
When we add checking for the timeout errors in a later patch, waiting for
EOCZ high would cause bogus time out errors.
Cc: Adam Ford <[email protected]>
Cc: Carl Philipp Klemm <[email protected]>
Cc: Eduardo Valentin <[email protected]>
Cc: H. Nikolaus Schaller <[email protected]>
Cc: Merlijn Wajer <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Peter Ujfalusi <[email protected]>
Cc: Sebastian Reichel <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
Tested-by: Adam Ford <[email protected]> #logicpd-torpedo-37xx-devkit
Acked-by: Pavel Machek <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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