diff options
| author | Sowjanya Komatineni <[email protected]> | 2020-12-21 13:17:31 -0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-01-06 13:09:27 +0000 |
| commit | b499779761278d6f5339daa230938211d98861ef (patch) | |
| tree | ce8680a9c047ba4c5c2a89f7bb61dcf14eaba9d4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 74523a5dae0c96d6503fe72da66ee37fd23eb8f5 (diff) | |
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions