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| author | Dan Williams <dan.j.williams@intel.com> | 2022-11-29 10:48:12 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 13:40:16 -0800 |
| commit | af2dfef854aa6afdf380e15e39d936d3b66097f1 (patch) | |
| tree | 64b673c97aa3bf9f04ba9487d77a133de767c72a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | f0c4d9fc9cc9462659728d168387191387e903cc (diff) | |
cxl/pci: Cleanup repeated code in cxl_probe_regs() helpers
Rather then duplicating the setting of valid, length, and offset for
each type, just convey a pointer to the register map to common code.
Yes, the change in cxl_probe_component_regs() does not save
any lines of code, but it is preparation for adding another component
register type to map (RAS Capability Structure).
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974409293.1608150.17661353937678581423.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions