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| author | Inochi Amaoto <[email protected]> | 2024-10-24 14:21:02 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2024-11-04 02:02:19 +0100 |
| commit | a54108ca42eabb54d34674c790d06d07256f570d (patch) | |
| tree | f2915f26115a6ca557f3eed1c604bc2b9322f523 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 2fb3a142c6874353e5b1711034c790a25ef22cc9 (diff) | |
dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts
The UART of SG2044 is modified version of the standard Synopsys
DesignWare UART. The UART on SG2044 relys on the internal divisor
and can not set right clock rate for the common bitrates.
Add compatibles string for the Sophgo SG2044 uarts.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions