dt-bindings: clock: si5351: add PLL reset mode property

For applications where the PLL must be adjusted without glitches in the
clock output(s), a new silabs,pll-reset-mode property is added. It
can be used to specify whether or not the PLL should be reset after
adjustment. Resetting is known to cause glitches.

For compatibility with older device trees, it must be assumed that the
default PLL reset mode is to unconditionally reset after adjustment.

Cc: Sebastian Hesselbarth <[email protected]>
Cc: Rabeeh Khoury <[email protected]>
Cc: Jacob Siverskog <[email protected]>
Cc: Sergej Sawazki <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Alvin Šipraga <[email protected]>
Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-2-69b82311cb90@bang-olufsen.dk
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions