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| author | Yevgeny Kliteynik <[email protected]> | 2021-07-04 17:48:24 +0300 |
|---|---|---|
| committer | Saeed Mahameed <[email protected]> | 2021-08-26 15:38:03 -0700 |
| commit | 990467f8afde8c85215f6f4ab439b9615fd151e7 (patch) | |
| tree | 52f06a814a177d45b45ba2e9cff4e8969f8e79c0 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 63b85f49c05af3cc2dea6c4e0cfbac3786b3c638 (diff) | |
net/mlx5: DR, Skip source port matching on FDB RX domain
The FDB RX pipe is connected to the wire and the source port for all
incoming packets equals to wire, single uplink port per PF, this means
there is no point of matching on the source port in such case.
Once we recognize such case, we will optimize the RX steering rule.
Note that in such case we clean both source_eswitch_owner_vhca_id and
source_port.
Signed-off-by: Alex Vesker <[email protected]>
Signed-off-by: Yevgeny Kliteynik <[email protected]>
Reviewed-by: Alex Vesker <[email protected]>
Signed-off-by: Saeed Mahameed <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions