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| author | Raymond Yang <[email protected]> | 2020-12-17 09:24:30 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-01-13 23:44:06 -0500 |
| commit | 96b5e3e1f8b5d1e193e3ffc2250178f143f4d9c8 (patch) | |
| tree | 29d68bb80a8d170e110d323ef79501dcabd98935 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | cf3a2627597794797ce5930537c0e75df284b6e9 (diff) | |
drm/amd/display: fix seamless boot stream adding algorithm
[Why]
Seamless boot stream has hw resource assigned, already. 'add' is
actually rebuild the assignment.
[How]
Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx
matches
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Raymond Yang <[email protected]>
Reviewed-by: Martin Leung <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions