diff options
| author | Rex Zhu <[email protected]> | 2018-08-16 11:36:38 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2018-08-27 11:09:41 -0500 |
| commit | 9650205a32e7f69c9846a205351e307ea525c1e7 (patch) | |
| tree | 40e2846419a1788011722692bb53b1d3a18c18b4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | a3d9103ebfa03824d255060fc2c11ac94e3ef441 (diff) | |
drm/amd/display: Fix bug use wrong pp interface
Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.
Pointed out by Francis David <[email protected]>
v2: dal only need to set min_dcefclk and min_fclk to smu.
so use display_clock_voltage_request interface,
instand of update all display configuration.
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions