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| author | Jai Luthra <j-luthra@ti.com> | 2024-02-20 11:48:02 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2024-02-21 22:24:17 +0530 |
| commit | 90a67583171f213711de662fab9f8d24a2d291a9 (patch) | |
| tree | b244c9c9df8041229916a73ef11ce08d79df5487 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 2e53b9c05a1589577565625fdb45cf918b54eb39 (diff) | |
arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS
The INTR module for DMASS1 (CSI specific DMASS) is outside the currently
available ranges, as it starts at 0x4e400000. So fix the ranges property
to enable programming the interrupts correctly.
Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs")
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20240220-am62p_csi-v2-1-3e71d9945571@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions