diff options
| author | Sung Lee <[email protected]> | 2020-11-13 13:34:55 -0500 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-12-01 16:03:20 -0500 |
| commit | 901c1ec05ef277ce9d43cb806a225b28b3efe89a (patch) | |
| tree | e8e5f381e159ab20765995529926d49d3e8ac5d1 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 00b0ac67811b96d32940fa705fb1405139bb3aab (diff) | |
drm/amd/display: Update dram_clock_change_latency for DCN2.1
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
does that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.
[HOW]
Update latency from 23.84 to 11.72.
Signed-off-by: Sung Lee <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Aurabindo Pillai <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions