diff options
| author | Esben Haabendal <[email protected]> | 2024-08-14 12:37:26 +0200 |
|---|---|---|
| committer | Robert Foss <[email protected]> | 2024-08-19 15:36:47 +0200 |
| commit | 8a879141dcd15d2db876ce3adf88b9b01650b7fa (patch) | |
| tree | e588d924616ae0e42468c06e36ef481bd67781a4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 11c742bb5a26d4adc873f6e6e2b69a59e1eae285 (diff) | |
drm/bridge: nwl-dsi: Use vsync/hsync polarity from display mode
Using the correct bit helps. The documentation specifies bit 0 in both
registers to be controlling polarity of dpi_vsync_input and
dpi_hsync_input polarity. Bit 1 is reserved, and should therefore not be
set.
Tested with panel that requires active high vsync and hsync.
Signed-off-by: Esben Haabendal <[email protected]>
Reviewed-by: Robert Foss <[email protected]>
Signed-off-by: Robert Foss <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions