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| author | Vijendar Mukunda <Vijendar.Mukunda@amd.com> | 2024-08-13 16:29:44 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-08-13 12:39:19 +0100 |
| commit | 897e91e995b338002b00454fd0018af26a098148 (patch) | |
| tree | f6a363759597d13126af6da2ca029a32be67583d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | c56ba3e44784527fd6efe5eb7a4fa6c9f6969a58 (diff) | |
ASoC: SOF: amd: Fix for incorrect acp error register offsets
Addition of 'dsp_intr_base' to ACP error register offsets points to
wrong register offsets in irq handler. Correct the acp error register
offsets. ACP error status register offset and acp error reason register
offset got changed from ACP6.0 onwards. Add 'acp_error_stat' and
'acp_sw0_i2s_err_reason' as descriptor fields in sof_amd_acp_desc
structure and update the values based on the ACP variant.
>From Rembrandt platform onwards, errors related to SW1 Soundwire manager
instance/I2S controller connected on P1 power tile is reported with
ACP_SW1_I2S_ERROR_REASON register. Add conditional check for the same.
Fixes: 96eb81851012 ("ASoC: SOF: amd: add interrupt handling for SoundWire manager devices")
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20240813105944.3126903-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions