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author | Arnd Bergmann <arnd@arndb.de> | 2022-11-22 15:27:59 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2022-11-22 15:28:00 +0100 |
commit | 862fe29b89b319d511709dd9e51d7b5ab97b8683 (patch) | |
tree | 6250bd53c5cdb91e6bbd7a81829db6bbf6542f86 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | fe04716e1716b56de90e6065505c938cc027866d (diff) | |
parent | 8fbf94fea0b4e187ca9100936c5429f96b8a4e44 (diff) |
Merge tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V SoC drivers for v6.2
SiFive:
- add probe error handling to the ccache driver
* tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()
soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()
Link: https://lore.kernel.org/r/Y3u0Oydiv2Wauda2@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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