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| author | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 14:43:29 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 14:43:29 -0800 |
| commit | 7db0aa8cc019f4f926c19989d1c8696d3893d77c (patch) | |
| tree | b8043fa06a46388ff2df9d4a8708576569ed5a79 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | f0c4d9fc9cc9462659728d168387191387e903cc (diff) | |
| parent | f350c68e3cd5ce605e44c7830029cd936a223f66 (diff) | |
Merge "ACPICA: Add CXL 3.0 structures..." into for-6.2/cxl-xor
Pick up:
f350c68e3cd5 ("ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table")
...to build the new XOR interleave math support for the CXL Fixed Memory
Window Structures.
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions