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| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-11-29 16:12:18 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-12-03 15:53:42 +0200 |
| commit | 70a057b7d42582dc846be3d0502dde7e2bd33914 (patch) | |
| tree | 70ee3cd8a7d55eb4ee77256048350de87fce5fd0 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 1dd07e56a3f1b38a68f3dbd263a4badc53ae274a (diff) | |
drm/i915/icl: Calculate DPLL params for DSI
This patch calculates various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.
v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
v3: Rebase
v4: use port clock instead of bitrate.
v5: Reabse and remove divide by 5
v6 by Jani:
- Fix indent (Madhav)
- Fix dpll state calc for EDP and DP MST
Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions