Merge patch series "Support Zve32[xf] and Zve64[xfd] Vector subextensions"

Andy Chiu <andy.chiu@sifive.com> says:

The series composes of two parts. The first part Specifically,
patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
vlenb is observed by the system. Patch 2 fixes the issue by failing the
boot process of a secondary core if vlenb mismatches.

Here is the organization of the series:
 - Patch 1, 2 provide a fix for mismatching vlen problem [1]. The
   solution is to fail secondary cores if their vlenb is not the same as
   the boot core.
 - Patch 3 is a cleanup for introducing ZVE* Vector subextensions. It
   gives the obsolete ISA parser the ability to expand ISA extensions for
   sigle letter extensions.
 - Patch 4, 5, 6 introduce Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa
   parsing and hwprobe, and document about it.
 - Patch 7 makes has_vector() check against ZVE32X instead of V, so most
   userspace Vector supports will be available for bare ZVE32X.
 - Patch 8 updates the prctl test so that it runs on ZVE32X.

The series is tested on a QEMU and verified that booting, Vector
programs context-switch, signal, ptrace, prctl interfaces works when we
only report partial V from the ISA.

* b4-shazam-lts:
  selftest: run vector prctl test for ZVE32X
  riscv: vector: adjust minimum Vector requirement to ZVE32X
  riscv: hwprobe: add zve Vector subextensions into hwprobe interface
  riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
  dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
  riscv: cpufeature: call match_isa_ext() for single-letter extensions
  riscv: vector: add a comment when calling riscv_setup_vsize()
  riscv: smp: fail booting up smp if inconsistent vlen is detected

[Palmer: reorder the first two patches so I can merge the fix, and
rebase this on v6.10-rc1 so it's a little easier to manage.]

Link: https://lore.kernel.org/r/20240510-zve-detection-v5-0-0711bdd26c12@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

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