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| author | Biju Das <[email protected]> | 2022-04-30 12:41:49 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-05-05 12:10:21 +0200 |
| commit | 6cc859cae9aa8c42e8347e2806232bdffeb1b33d (patch) | |
| tree | cddfa732f740cf19681215f34424b31f32c5f058 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 1561380ee72f55e3a86856ee046532c18d3e9855 (diff) | |
clk: renesas: rzg2l: Add PLL5_4 clk mux support
Add PLL5_4 clk mux support to select clock from clock
sources FOUTPOSTDIV and FOUT1PH0.
Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions