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| author | Tony Lindgren <tony@atomide.com> | 2024-03-27 09:10:37 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2024-04-10 09:15:43 +0300 |
| commit | 6c95cd7a40c460373a42e6f617f3e4d756f5acbd (patch) | |
| tree | a66132c2a80962b960a392b624250094348f9a91 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d3c9a44103e98f2722c8b8c48b604995f5063034 (diff) | |
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions