diff options
| author | Mauro Rossi <[email protected]> | 2019-05-26 17:31:42 +0200 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-07-27 16:45:55 -0400 |
| commit | 683b59504d4ecec3251a23fdac7e8775385a18c5 (patch) | |
| tree | ac08c23d53eb85e9a6a824549332aaf5d3a98d9a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 7c15fd86aaec3e602e140c242369df2baddc865e (diff) | |
drm/amd/display: dc/core: add SI/DCE6 support (v2)
[Why]
resource_parse_asic_id() and dc_create_resource_pool() are missing SI/DCE6 cases
[How]
SI/DCE6 cases support added using existing DCE8 implementation as a reference
(v2) updated due to following kernel 5.2 commit:
d9673c9 ("drm/amd/display: Pass init_data into DCN resource creation")
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Mauro Rossi <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions