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authorStefan Agner <[email protected]>2019-07-29 12:52:03 -0700
committerGreg Kroah-Hartman <[email protected]>2019-09-04 12:43:46 +0200
commit656321793ff419eda148d91dd02b167d6da819e4 (patch)
tree37b9b479cece4a26099f470f809feaf3a1dda23b /tools/perf/scripts/python/export-to-sqlite.py
parentb777b5de6aaa98df37c0fe1f7a33fa1c63d0e326 (diff)
tty: serial: fsl_lpuart: fix framing error handling when using DMA
When using DMA framing error get cleared properly. However, due to the additional read from the data register, an underflow in the receive FIFO buffer occurs (the FIFO pointer gets out of sync). Clear the FIFO in case an underflow has occurred. Also disable the receiver during this operation and when reading the data register to minimize potential interference. Signed-off-by: Stefan Agner <[email protected]> Acked-by: Max Krummenacher <[email protected]> Signed-off-by: Andrey Smirnov <[email protected]> Cc: Stefan Agner <[email protected]> Cc: Bhuvanchandra DV <[email protected]> Cc: Chris Healy <[email protected]> Cc: Cory Tusar <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: Jiri Slaby <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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