diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-02-21 12:18:36 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2023-02-27 09:14:57 -0800 |
| commit | 5767dc9e2df70550552c856ebc4b8467767661f6 (patch) | |
| tree | 9e2c52217d477431542d7561d4e8328c83a899c8 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | c6a53c90e3be8b7e745a46c941631d0855648313 (diff) | |
drm/i915/gen12: Update combo PHY init sequence
The bspec was updated with a minor change to the 'DCC mode select'
setting to be programmed during combo PHY initialization.
v2:
- Keep the opencoded rmw behavior instead of switching to
intel_de_rmw(). We need to read from a _LN register, but write to
the _GRP register to update all lanes.
Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230221201836.2886794-1-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions