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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2020-10-15 22:03:29 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-11-04 08:26:25 -0800 |
| commit | 5047ab95bb7db0e7b2ecfd5e9bcafc7fd822c652 (patch) | |
| tree | e5af3107970c427b9100d2b50e1a3cfd8ab234c4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 91693cbc13c2eebaa2bffb685cc7cb6d561f33ec (diff) | |
drm/msm/dsi_pll_7nm: restore VCO rate during restore_state
PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions