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| author | Huacai Chen <[email protected]> | 2022-05-31 18:04:10 +0800 |
|---|---|---|
| committer | Huacai Chen <[email protected]> | 2022-06-03 20:09:27 +0800 |
| commit | 439057ec3b748b1ff61855d09859f369493e22d8 (patch) | |
| tree | 488f331128a8ba653855b4434dcf1825b12804bb /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 08145b087e4481458f6075f3af58021a3cf8a940 (diff) | |
LoongArch: Add writecombine support for drm
LoongArch maintains cache coherency in hardware, but its WUC attribute
(Weak-ordered UnCached, which is similar to WC) is out of the scope of
cache coherency machanism. This means WUC can only used for write-only
memory regions.
Cc: Daniel Vetter <[email protected]>
Cc: [email protected]
Reviewed-by: WANG Xuerui <[email protected]>
Reviewed-by: Jiaxun Yang <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions