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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-11-15 10:51:34 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-17 20:27:02 +0100 |
| commit | 42d3345eb3466587798c25a7e5704e15b738263e (patch) | |
| tree | 1061e812593ac1a1d1530f6338dd88e03e575ff5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 461e1857d6bf15cf5df103383e255f3425ac0038 (diff) | |
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM:
- ADC
- OPP
- Thermal Zones
- TSU
Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them
here too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions