diff options
| author | Shengjiu Wang <[email protected]> | 2023-05-05 15:55:22 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2023-05-08 08:48:53 +0900 |
| commit | 3e4a826129980fed0e3e746a7822f2f204dfc24a (patch) | |
| tree | 9da7a1e787731b8eaec00f7111fb8a0f6e3296f3 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 101b23830d3c26e9549274d16e8d4542c8bce4af (diff) | |
ASoC: fsl_sai: MCLK bind with TX/RX enable bit
On i.MX8MP, the sai MCLK is bound with TX/RX enable bit,
which means the TX/RE enable bit need to be enabled then
MCLK can be output on PAD.
Some codec (for example: WM8962) needs the MCLK output
earlier, otherwise there will be issue for codec
configuration.
Add new soc data "mclk_with_tere" for this platform and
enable the MCLK output in startup stage.
As "mclk_with_tere" only applied to i.MX8MP, currently
The soc data is shared with i.MX8MN, so need to add
an i.MX8MN own soc data with "mclk_with_tere" disabled.
Signed-off-by: Shengjiu Wang <[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions