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author | Lad Prabhakar <[email protected]> | 2024-06-04 18:05:13 +0100 |
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committer | Greg Kroah-Hartman <[email protected]> | 2024-06-24 16:09:37 +0200 |
commit | 2f50304e9efb69604040feadc13f9590be8cd391 (patch) | |
tree | 752d3a3d1cc2d59991710f0b0a45f56919308a59 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 964a80cfbf56f5fa88f09d704c311ed6db0a361f (diff) |
serial: sh-sci: Add support for RZ/V2H(P) SoC
Add serial support for RZ/V2H(P) SoC with earlycon.
The SCIF interface in the Renesas RZ/V2H(P) is similar to that available
in the RZ/G2L (R9A07G044) SoC, with the following differences:
- RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready
and two for Rx and Tx buffer full, all of which are edge-triggered.
- RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both
synchronous and asynchronous modes.
- There are differences in the configuration of certain registers such
as SCSMR, SCFCR, and SCSPTR between the two SoCs.
To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE
is added.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions