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| author | Kishon Vijay Abraham I <[email protected]> | 2021-03-19 18:11:27 +0530 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2021-03-31 16:43:21 +0530 |
| commit | 28081b72859f0fa3d5b56cfd84b2f5ba578765d2 (patch) | |
| tree | 79304aaaab9c7c871f79771c9bfafb630f1dac59 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | db7a346405dc71be0c4ad7f39dd7978d4d20dee0 (diff) | |
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Reviewed-by: Swapnil Jakhade <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions