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| author | Arnd Bergmann <arnd@arndb.de> | 2022-11-21 11:53:45 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-11-21 15:03:08 +0100 |
| commit | 2092ad3a79ca6d987f994e8b9b72f9fde5f29aa8 (patch) | |
| tree | 849db6ea24873dddb28c4ac47c829205785a88db /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | f241625bb3aeb8aab3e2f67848456d55da529564 (diff) | |
| parent | 40005cb6093e92d24a1bdbc444311c25e4b28878 (diff) | |
Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas RISC-V DT updates for v6.2
- Add initial support for the Renesas RZ/Five SoC and the Renesas
RZ/Five SMARC EVK development board.
* tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
MAINTAINERS: Add entry for Renesas RISC-V
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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