diff options
| author | Ashutosh Dixit <[email protected]> | 2023-04-20 09:40:40 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2023-04-26 18:02:40 -0400 |
| commit | 1b44019a93e2bc6088d777b3d3072df5f40f9324 (patch) | |
| tree | b9691c2864b4513aafe2bdc4c18500f470fcffaa /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d81268ee1c1073471cf0e8adb0fc9d026b602c3b (diff) | |
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
On dGfx, the PL1 power limit being enabled and set to a low value results
in a low GPU operating freq. It also negates the freq raise operation which
is done before GuC firmware load. As a result GuC firmware load can time
out. Such timeouts were seen in the GL #8062 bug below (where the PL1 power
limit was enabled and set to a low value). Therefore disable the PL1 power
limit when allowed by HW when loading GuC firmware.
v2:
- Take mutex (to disallow writes to power1_max) across GuC reset/fw load
- Add hwm_power_max_restore to error return code path
v3 (Jani N):
- Add/remove explanatory comments
- Function renames
- Type corrections
- Locking annotation
v4:
- Don't hold the lock across GuC reset (Rodrigo)
- New locking scheme (suggested by Rodrigo)
- Eliminate rpm_get in power_max_disable/restore, not needed (Tvrtko)
v5:
- Fix uninitialized pl1en variable compile warning reported by kernel
build robot by creating new err_rps label
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit <[email protected]>
Reviewed-by: Rodrigo Vivi <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions