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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-04-17 20:41:25 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-04-29 10:26:53 +0200 |
| commit | 0d3051c790ed2ef6bd91b92b07220313f06b95b3 (patch) | |
| tree | 21b9d75c000618066474a67d8d07eb096e3dd753 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | da1978ac3d6cf278dedf5edbf350445a0fff2f08 (diff) | |
clk: meson: meson8b: Fix the polarity of the RESET_N lines
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means:
- asserting them requires setting the register value to 0
- de-asserting them requires setting the register value to 1
Set the register value accordingly for these two reset lines by setting
the inverted the register value compared to all other reset lines.
Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions