aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/export-to-sqlite.py
diff options
context:
space:
mode:
authorDmitry Osipenko <digetx@gmail.com>2021-09-30 01:28:05 +0300
committerThierry Reding <treding@nvidia.com>2021-12-16 14:07:07 +0100
commit0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c (patch)
tree503f22db3d777e19cdf04663606a6e66ded1f103 /tools/perf/scripts/python/export-to-sqlite.py
parent0f52fc3fc97d7e083f498f4be95b049dd94a6ef6 (diff)
drm/tegra: dc: rgb: Allow changing PLLD rate on Tegra30+
Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI bridge that requires a precise clock rate in order to operate properly. Tegra30 has a dedicated PLL for each display controller, hence the PLL rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB output. Configure the clock rate before display controller is enabled since DC itself may be running off this PLL and it's not okay to change the rate of the active PLL that doesn't support dynamic frequency switching since hardware will hang. Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions