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| author | Radhakrishna Sripada <[email protected]> | 2023-03-01 12:10:49 -0800 |
|---|---|---|
| committer | Radhakrishna Sripada <[email protected]> | 2023-03-09 09:40:17 -0800 |
| commit | 0188be507b973e36f637ba010a369057c8cb7282 (patch) | |
| tree | 82be942bda5816b14feb1a5d611cfbd36e1d67c6 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 4b736ed40583631e0cf32c55dbc1e5ec0434a74b (diff) | |
drm/i915/mtl: Fix Wa_16015201720 implementation
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.
Implement the workaround with the correct register.
v3: Skip clock gating for pipe C, D DMC's and fix the title
Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
Cc: Matt Atwood <[email protected]>
Cc: Lucas De Marchi <[email protected]>
Signed-off-by: Radhakrishna Sripada <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions