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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-02 10:51:41 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-06-02 10:51:41 -0700 |
| commit | f6b3130919eac29314f159563ebd3584821a294d (patch) | |
| tree | 1b4543d45c88ad8b1cf3c8a4921b7adf3517a15b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 8fedfee49fb57244df8d96de1478eed79f45bd83 (diff) | |
| parent | 14c735c8e3082714e3d5fa91843692a9c871cebe (diff) | |
Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clock driver updates from Jerome Brunet:
* Expose more i2s and spdif output clocks
* Expose EE uart and SPICC gate clocks
* Remove cpu_clk from to gxbb
* Mark clk81 as critical on gxbb
* Add CEC EE clocks
* tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson:
clk: meson-gxbb: Add EE 32K Clock for CEC
clk: gxbb: remove CLK_IGNORE_UNUSED from clk81
clk: meson: meson8b: mark clk81 as critical
clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver
clk: meson-gxbb: un-export the CPU clock
clk: meson-gxbb: expose UART clocks
clk: meson-gxbb: expose SPICC gate
clk: meson-gxbb: expose spdif master clock
clk: meson-gxbb: expose i2s master clock
clk: meson-gxbb: expose spdif clock gates
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions