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| author | Aric Cyr <[email protected]> | 2024-05-05 22:28:31 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-05-13 15:48:14 -0400 |
| commit | f45957432351b58a77fab63989ca842c314847b4 (patch) | |
| tree | 2dc8a81fcb36ed459a92b8069839401dc757e1e1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | fa73ec95c969c7af292caf622ef499e7af7cb062 (diff) | |
drm/amd/display: 3.2.285
This version brings along following fixes:
- Read default boot options
- Find max flickerless instant vtotal delta
- Refactor dcn401_update_clocks
- Reduce I2C speed to 95kHz in DCN401
- Allow higher DSC slice support for small timings on dcn401
- Don't offload flip if not only address update
- Check UHBR13.5 cap when determining max link cap
- Enable SYMCLK gating in DCCG
- Expand to higher link rates
- Add left edge pixel for YCbCr422/420 + ODM pipe split
- Add resource interfaces for get ODM slice rect
- Add COEF filter types for DCN401
- Refactor DCN401 DCCG into component directory
- Fix 3dlut size for Fastloading on DCN401
- Fix write to non-existent reg on DCN401
- Remove USBC check for DCN32
- Remove unused code for some dc files
- Disable AC/DC codepath when unnecessary
- Create dcn401_clk_mgr struct
Acked-by: Alex Hung <[email protected]>
Signed-off-by: Aric Cyr <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions