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authorHeiko Stuebner <heiko.stuebner@vrull.eu>2024-01-21 16:19:12 -0800
committerPalmer Dabbelt <palmer@rivosinc.com>2024-01-22 17:55:15 -0800
commitdf513ed49f0073ce1778eb469ab5db44bceade30 (patch)
tree8d88f21b7c57477092c363fdd721f38deae82695 /tools/perf/scripts/python/export-to-postgresql.py
parent6613476e225e090cc9aad49be7fa504e290dd33d (diff)
RISC-V: add helper function to read the vector VLEN
VLEN describes the length of each vector register and some instructions need specific minimal VLENs to work correctly. The vector code already includes a variable riscv_v_vsize that contains the value of "32 vector registers with vlenb length" that gets filled during boot. vlenb is the value contained in the CSR_VLENB register and the value represents "VLEN / 8". So add riscv_vector_vlen() to return the actual VLEN value for in-kernel users when they need to check the available VLEN. Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20240122002024.27477-2-ebiggers@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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