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authorThomas Zimmermann <[email protected]>2020-05-15 10:32:23 +0200
committerThomas Zimmermann <[email protected]>2020-05-19 09:41:33 +0200
commitdb05f8d3dc875249a5a11737ca715584b72851e8 (patch)
tree1368d029ea3fe4dfb02f2a5582f167f9707cfd5c /tools/perf/scripts/python/export-to-postgresql.py
parenta6edae07fd015c1a9af98477e1274cd4d489c1cb (diff)
drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O
Set different fields in MISC in their rsp location in the code. This patch also fixes a bug in the original code where the mode's SYNC flags were never written into the MISC register. v2: * use u8 instead of uint8_t * define MGAREG_MISC_CLK_SEL_MASK Signed-off-by: Thomas Zimmermann <[email protected]> Tested-by: John Donnelly <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Acked-by: Emil Velikov <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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