staging: comedi: adv_pci1710: fix counter 0 internal clock source

There are a number of descrepencies in the various manuals for the boards
that this driver supports. Some show a 10 MHz clock for counters 1 and 2
others show a 1 MHz clock. Counter 0 can use either a div 10 of that clock
or an external clock (up to 10 MHz).

Currently this driver initializes counters 1 and 2 with a 10 MHz clock.
For consistency, return 1 MHz (10 MHz/10) for counter 0 when the user
queries the internal clock source with INSN_CONFIG_GET_CLOCK_SRC.

Signed-off-by: H Hartley Sweeten <[email protected]>
Reviewed-by: Ian Abbott <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

0 files changed, 0 insertions, 0 deletions