aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/export-to-postgresql.py
diff options
context:
space:
mode:
authorAndre Przywara <andre.przywara@arm.com>2020-09-07 13:18:26 +0100
committerWei Xu <xuwei5@hisilicon.com>2020-09-14 16:15:22 +0800
commitc26979a7acf20ab093513d8c09e371b212e02ded (patch)
treeaaee15880d2c382f65069b630ca28df6f53a1550 /tools/perf/scripts/python/export-to-postgresql.py
parent9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff)
ARM: dts: hisilicon: Fix SP804 users
The SP804 binding only specifies one or three clocks, but does not allow just two clocks. The HiSi 3620 .dtsi specified two clocks for the two timers, plus gave one "apb_pclk" clock-name to appease the primecell bus driver. Extend the clocks by duplicating the first clock to the end of the clock list, and add two dummy clock-names to make the primecell driver happy. I don't know what the real APB clock for the IP is, but with the current DT the first timer clock was used for that, so this change keeps the current status. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions