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| author | Dharageswari.R <[email protected]> | 2016-02-05 12:19:07 +0530 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2016-02-08 16:44:17 +0000 |
| commit | c115fa5ec06a647c5aeff95d73e56d488145ec2e (patch) | |
| tree | b278c825a2ead41cbd4a7a2631e3b5d4b28108f0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 718a42b5eaddb3180e2589590732d61e047858fb (diff) | |
ASoC: Intel: Skylake: Add MCLK configuration
The SoC has MCLK output which is typically required by codecs.
The MCLK is controlled by DSP FW, so driver can configure that by
sending DMA_CONTROL IPC. The configuration for MCLK is present
in the endpoint blob.
So if block has this configuration, send IPC to DSP for MCLK
configuration. This is done by new function skl_dsp_set_dma_control()
which is invoked by BE prepare.
Signed-off-by: Dharageswari R <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions