diff options
| author | Owen Chen <owen.chen@mediatek.com> | 2019-03-05 13:05:38 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-11 13:09:17 -0700 |
| commit | be17ca6ac76a5cfd07cc3a0397dd05d6929fcbbb (patch) | |
| tree | e023d9e521b7565640d18eb0425cc51ac1a88bb5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff) | |
clk: mediatek: Disable tuner_en before change PLL rate
PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.
Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
Cc: <stable@vger.kernel.org>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions