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| author | Ville Syrjälä <[email protected]> | 2016-03-15 16:40:05 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2016-04-12 21:12:02 +0300 |
| commit | ae9ec62bdadc4cd3bf893d6baced80aa3a5dbbd6 (patch) | |
| tree | 97329e1675016aa44a43ebb7eccbb378ff473e35 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | f00b56896ec2443a33277f5411de0cbd13071cec (diff) | |
drm/i915: Fix CHV DSI PLL refclk during state readout
Use the proper refclock frequency (100MHz) when reading out the
current DSI clock on CHV.
Signed-off-by: Ville Syrjälä <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions