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| author | Kyle Russell <[email protected]> | 2021-06-21 21:09:41 -0400 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-07-01 14:50:28 +0100 |
| commit | 9cf76a72af6ab81030dea6481b1d7bdd814fbdaf (patch) | |
| tree | 55b6878f09aab0c11c367e046e7b8462f2380e36 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 2c70ff56e49ae219640689a0c86041c0f656046f (diff) | |
ASoC: tlv320aic31xx: fix reversed bclk/wclk master bits
These are backwards from Table 7-71 of the TLV320AIC3100 spec [1].
This was broken in 12eb4d66ba2e when BCLK_MASTER and WCLK_MASTER
were converted from 0x08 and 0x04 to BIT(2) and BIT(3), respectively.
-#define AIC31XX_BCLK_MASTER 0x08
-#define AIC31XX_WCLK_MASTER 0x04
+#define AIC31XX_BCLK_MASTER BIT(2)
+#define AIC31XX_WCLK_MASTER BIT(3)
Probably just a typo since the defines were not listed in bit order.
[1] https://www.ti.com/lit/gpn/tlv320aic3100
Signed-off-by: Kyle Russell <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions