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| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2018-12-14 09:10:13 +0000 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2019-01-22 15:42:27 +0100 |
| commit | 9b55a05ebfbe41bfb4c2aa98a81a46f2031e599f (patch) | |
| tree | 79bcbb71491978f7671aa63fb335a3ffdc48f756 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 8d68821ced28391551b5e2014de4b1bf461b667e (diff) | |
arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core
Add a device node for the second Cortex-A53 CPU core on the Renesas
RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
for the ARM Generic Interrupt Controller and Architectured Timer.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions